1. Field of the Invention
The present invention relates to a delay locked loop circuit, in which a synchronous loop is formed with delay elements.
2. Description of the Related Art
A data signal is often transferred in synchronization with a clock signal in order to surely transmit and receive the data signal between circuit blocks. In recent years, the frequency of the clock signal increases so that the circuit blocks operate at a higher speed. In order to avoid a problem of a clock skew caused due to the increase in clock frequency or a problem of measurement of a variety of transfer modes, apparatuses increase in which phase relationship of the clock signals is different between a data transmission side and a data reception side. A delay locked loop (“DLL”) circuit can generate clock signals having such different phases.
For example, Japanese Laid Open Patent Application (JP-P2004-62578A) discloses a multi-phase clock generating circuit, which generates multi-phase clock signals having optional phases by use of a PLL (phase locked loop) circuit and a DLL circuit. The multi-phase clock generating circuit is composed of a multi-phase output oscillating circuit, an interpolator (a phase interpolating circuit), a first control circuit, a frequency divider, a phase shifter, a first phase comparator, a second phase comparator, and a second control circuit. The multi-phase clock generating circuit generates a feedback clock signal different in X-phase with respect to a reference clock signal. The multi-phase output oscillating circuit supplies an output clock signal to the phase interpolating circuit. The phase interpolating circuit has a mechanism of outputting a 0-phase output signal serving as a reference signal and an optional X-phase output signal which is controllably set based on a signal from an external terminal. The first control circuit has an external terminal, to which a signal can be supplied to set an optional Y-phase with respect to the reference clock signal, and outputs a control signal for setting an optional X-phase output signal with respect to a multiple clock signal to the phase interpolating circuit. Furthermore, the first control circuit outputs a phase shift count of a phase shifter and a select signal for selecting an input of phase shift data at the same time. The frequency divider frequency-divides the 0-phase output signal serving as the reference signal from the phase interpolating circuit, and has a mechanism of setting a frequency division ratio. The phase shifter receives the frequency-divided clock signals of two different phases from the frequency divider at its phase shift data inputs, and supplies the optional X-phase output clock signal outputted from the phase interpolating circuit to the phase shift clock input. Moreover, the phase shifter selects one of the shift counts with respect to the phase shift clock signal. The first phase comparator compares a phase of the reference clock signal with a phase of the frequency-divided output signal from the frequency divider, and controls an oscillation frequency of the multi-phase output oscillating circuit. The second phase comparator regards an X-phase of a signal outputted through the phase shifter as a reference of delay in the delay circuit. The second control circuit incorporates therein a delay value of a reference clock delay circuit. The multi-phase output clock generating circuit outputs a delay circuit control setting value from the second control circuit to the outside.
That is to say, the phase comparator compares the phase of the clock signal obtained by frequency dividing the clock signal from the multi-phase output oscillating circuit by the frequency divider with the phase of the reference clock signal. The multi-phase output oscillating circuit is controlled such that the above-mentioned two phases match with each other. Additionally, the phase of the-clock signal outputted from the multi-phase output oscillating circuit is interpolated by the phase interpolating circuit, so that a delay clock signal is generated to have an optional phase delay. The first phase comparator compares the phase of the clock signal obtained by delaying the reference clock signal by the delay circuit with the phase of the delayed clock signal. A delay time in the delay circuit is controlled based on the comparison result. In other words, the delay time in the delay circuit is controlled to have a predetermined delay time. A slave DLL circuit is provided, in which the delay time has been controlled by a master DLL circuit.
Otherwise, Japanese Laid Open Patent Application (JP-P2001-339280A) discloses a specific circuit configuration of a phase interpolating circuit. According to this circuit configuration, the phase interpolating circuit is constituted of a timing difference dividing circuit.
In this manner, the above-described multi-phase output clock generating circuit is provided with the multi-phase output oscillating circuit whose phase jitter influences on the delay time in the delay circuit. As a consequence, the phase jitter in the multi-phase output oscillating circuit influences on a delay time in a delay circuit on a slave side.